Nord Lead 3 problem, does not boot [SOLVED]

[pterm]

I see in the User Manual https://www.nxp.com/docs/en/data-sheet/MC68331UM.pdf Table 4-8, the settings allow 25.166MHZ (but this exceeds the allowed system maximum clock).

I wonder if the boot ROM is corrupt or malfunctioning and this programs the system clock incorrectly.
To test this idea please try to capture CSBOOT on one oscilloscope channel and CLKOUT on another. Use falling edge of CSBOOT to trigger. If you see CLKOUT = 8.389MHz during CSBOOT, and changing to 25.166MHz after boot, this suggests the problem exists in the boot ROM or on the interface between it and the MC68331.

[23skidoo]

The boot flash might just be bad, too, you know. Common issue - flash chips have a limited retention lifespan often around 20 years. Would be nice if someone here had an image of that chip so we could just burn our own to be sure. I don't have a chip clamp and reader, though. What makes you so sure it's the MCU? And why did you replace the capacitors before verifying they were a problem? I find that reworking older boards can often *cause* more damage to adjacent already-age-marginal components, so I strongly advise against it until you are certain of the part that has failed.

** Edit: Ah, sorry pterm didn't see the second page of comments and you said basically the same thing. **

[hozone]

Really thank you all.

@pterm
It's again a bit weired signal, find the images attached (yellow CLKOUT, blue CSBOOT) from 1 to 7 in order of signal time (bottom up in this post)
CLKOUT starts after 25msec.
Starts as a square with some triangles (that can be due to scope).
It slowly (I've not enough buffer but i think 1 or 2 sec) became a 25Mhz signal. At some point oscillating at 6.8Mhz almost (last 2 images).

It's just an idea... can it be a DSP damaged that "clock out" on the clock line?
Another think I've notice is that the CMOS (27SF010) only output on DQ0 and DQ1, something like the attached image

@23skidoo
I just change caps cause "most of the time they are the faulty one I know I shouldn't but I'm a bit lost now.

@maxpiano, I've try this with no luck

[pterm]

Hi hozone,
Thanks for capturing all those images. Unfortunately, they create more questions than answers. I hope these captures occurred too early before the CLKOUT stabilized.
Please select "Falling" trigger for Ch2 (CSBOOT). CSBOOT should only go low if the CLKOUT is stable (if I understand the documentation correctly). Please check if your settings match those I highlighted in the images below.

Sorry to ask you repeat the measurements, but I hope to find something that identifies the cause of the boot problem.

[hozone]

First of all thank you for your help.
Find attached the images.
On falling edge of CSBOOT, it goes up again.
During the a first stage CSBOOT is HIGH, and CLKOUT is 8Mhz or so, like it should be.
CSBOOT the goes doen and high every 2us almost, we are in 8Mhz ok range here.
After 80us almost CLKOUT double 16Mhz or so, and CSBOOT double is speed.
My scope mem ends here, I can attach this to a logic analyzer if need, but i think It could be the CMOS like you suppose.
Another thing I've notice is that there are times (most of the times not) that the same measurement end up with starts with a clock out of 1.5Mhz and ends with a clock of 900Khz or so (???) - attached the ending image, maybe my mistake?
What do you think?

[pterm]

First of all thank you for your help.
Find attached the images.
On falling edge of CSBOOT, it goes up again.
During the a first stage CSBOOT is HIGH, and CLKOUT is 8Mhz or so, like it should be.
CSBOOT the goes doen and high every 2us almost, we are in 8Mhz ok range here.
After 80us almost CLKOUT double 16Mhz or so, and CSBOOT double is speed.
My scope mem ends here, I can attach this to a logic analyzer if need, but i think It could be the CMOS like you suppose.
Another thing I've notice is that there are times (most of the times not) that the same measurement end up with starts with a clock out of 1.5Mhz and ends with a clock of 900Khz or so (???) - attached the ending image, maybe my mistake?
What do you think?

Prego.
The image CSBOOT_start_changetime.jpg shows what I expected: the clock changing from 8MHz to about 16MHz. This shows us that the MCU attempts to boot and gets as far as programming its internal oscillator (at least sometimes).

Regarding the times when you see "clock out of 1.5Mhz and ends with a clock of 900Khz or so" -- please check the sampling rate: Sampling Rate (see image) needs to be greater than 32MSa/sec to obtain a meaningful capture a 16MHz clock. Some oscilloscopes dynamically change the sampling rate depending on the memory depth setting and the time/division setting ("horizontal time base"). If the sampling rate drops below 2 X the frequency being measured "aliasing" occurs and the representation of the signal shown on the screen misrepresents reality.

If you find the clock measurement of "clock out of 1.5Mhz and ends with a clock of 900Khz or so" is valid (>32MSa/sec sampling rate), this might indicate a problem with either the MCU's oscillator. Check the RESET level - the MCU User Manual says it asserts RESET (low) until its oscillator locks.

What logic analyzer make/model do you have?
I did not find a timing diagram for the MCU boot sequence, so I do not advise any logic analyzer captures yet. I need to understand your logic analyzer's capabilities before I can recommend if and how to make such a capture.

[hozone]

Thanks.
I will check the 1.5Mhz / sampling rate this evening at home, and repeat measurment with more consistency.
My logic is something like this https://sigrok.org/wiki/VKTECH_saleae_clone - I've never used this for things up to 1Mhz, always for SPI and I2C, so I don't know about the 24Mhz max specs, but I think it could do this.

[oliverbajza]

Probably you did try this but if not: what happens if you press and hold STORE and PERFORMANCE MODE while turning the synth on? Maybe the firmware needs to be
installed again?

[hozone]

Time sample rate is 100MSa
Now i get consistent reading, 8Mhz at startup, then all goes fast. Repeated a few times. Think yesterday something when wrong maybe with ground. I was a bit hurry.
I now constantly get something like CSBOOT_start_changetime.jpg.
Another thing is that i can not find CSKOUT other than on DSP56362, and on all the DSL the signal is slightly changed (see attached), but it maybe due to the frequency of the signal.

@oliverbajza
tried it, no luck, it does not boot

[pterm]

My logic is something like this https://sigrok.org/wiki/VKTECH_saleae_clone - I've never used this for things up to 1Mhz, always for SPI and I2C, so I don't know about the 24Mhz max specs, but I think it could do this.

As far as I can tell, the CLK input pin to the VKTECH is sampled (rather than a trigger). Some (older) logic analyzers used the CLK input to sample/trigger the data - since the Nord's MCU boot interface lacks a clock I feared this might introduce problems.
This USB-style logic analyzer however effectively it has no memory limit and its internal sample clock (24MHz in the case above) means it also sample the CLK input pin, so I think it could capture the 8 data bits and the CSBOOT (into CLK input) if we decide to do that.